Design and Simulation of a Circuit to Predict and Compensate Performance Variability in Submicron Circuit

16 Abstract— This paper presents a technique for compensating process, voltage and temperature variations due to manufacturing and environmental variability in submicron circuits using canary flip-flop. This canary flip flop predicts the timing error before it actually occurs and compensate the performance so that the system performance does not get affected. I am going to design a 16-bit Brent-Kung adder in 45-nm CMOS technology , whose performance will be controlled by supply voltage scaling. We will show that this technique can compensate process, supply voltage, and temperature variations and improve the energy efficiency of submicron circuits. We also compare Power dissipation for Worst case design and performance compensate design and show performance design has less power dissipation when compared to worst case design.